1. Field of the Invention
The present invention relates to hard-disk drive systems and other recording systems, and, more specifically, to preamplifiers for such systems.
2. Description of the Related Art
FIG. 1 shows a block diagram of a conventional hard-disk (or disc) drive (HD) system 100 for writing data to and reading data from a disk platter 114. HD system 100 includes a data controller 102, a recording channel 104, a preamplifier 106, and a head assembly 108 comprising a write head 110 and a read head 112. Additionally, HD system 100 has a spindle motor 116, a voice coil motor (VCM) 118, and a motor controller 120 for controlling (1) the rotation of disk platter 114 by spindle motor 116 and (2) the radial position of head assembly 108 relative to the disk platter. Depending on storage capacity needs, HD system 100 may have multiple platters, each served by one or two additional heads.
Data controller 102 manages a number of functions in HD system 100. One function is handling the transfer of data to and from HD system 100 during read and write operations. During write operations, incoming digital data is received from external hardware through a user interface 122, such as a SATA (serial advanced technology attachment) or IDE (integrated or intelligent drive electronics) interface. Outgoing digital data is received in parallel format from recording channel 104. Both incoming and outgoing data are stored in queues in data controller 102 and scheduled for transfer operations. Outgoing data is transmitted to external hardware through user interface 122, while incoming data received from interface 122 is transmitted in parallel format to recording channel 104.
Another function of data controller 102 is the radial positioning of head assembly 108 relative to disk platter 114. Data controller 102 interprets servo data (i.e., positioning data that is prerecorded on and subsequently read from disk platter 114 by recording channel 104) and generates commands for motor controller 120 to position the head assembly.
Yet another function of data controller 102 is managing various operating modes of HD system 100. These operating modes, which are discussed later in greater detail, are triggered by data controller 102 and transmitted to preamplifier 106 via serial port lines 124.
Separate read and write functions are performed by recording channel 104. During write operations, recording channel 104 receives and modifies parallel, incoming data signals received from data controller 102. These modifications include conversion from digital to analog format, serialization, and encoding. The resulting modified data signals are then transmitted in serial format to preamplifier 106. During read operations, recording channel 104 receives and modifies serial, outgoing analog data signals from preamplifier 106. These modifications include decoding, digitization, and conversion to parallel format for transmission to data controller 102.
Preamplifier 106 also performs separate read and write functions. During write operations, preamplifier 106 receives incoming, analog data signals from recording channel 104, amplifies these signals, and transmits the resulting amplified signals to write head 110. Amplification occurs to a level that is sufficient to drive the inductive element of write head 110. During read operations, preamplifier 106 receives and amplifies small, reproduced analog data signals from read head 112 to a level sufficient for transmission to recording channel 104. In addition to data amplification and transmission, preamplifier 106 receives commands from data controller 102 via serial port lines 124 and other tags such as Write_Gate and Dummy_Select to trigger various operating modes, which will be discussed later in greater detail.
Write head 110 and read head 112 are typically separate components that are fabricated together as head assembly 108 on a single positioning arm 126. Write head 110 is typically constructed with an inductive element that produces a magnetic field when powered. Incoming analog data signals transmitted from preamplifier 106 supply sufficient power to write head 110 to generate the magnetic field. The analog signal level (e.g., high or low) determines the polarity of the magnetic field.
Read head 112 is typically constructed with a magneto-resistive (MR) element. The resistive properties of this MR head change as the magnetic field changes. A bias current is transmitted to the MR head from preamplifier 106, in order to establish head operating point for linear relation between resistance change and incident magnetic flux. As the resistive properties of the magneto-resistive element change, a corresponding change in voltage is recorded as a reproduced, or playback, analog data signal. This data signal is then transmitted from read head 112 back to preamplifier 106.
The positioning of write head 110 and read head 112 of head assembly 108 radially over disk platter 114 is performed by VCM 118. VCM 118 is driven by motor controller 120, which receives commands from data controller 102. Servo data on disk platter 114 is used to determine the location of read head 112 over disk platter 114. This data is interpreted by data controller 102, which sends positioning commands to motor controller 120. Motor controller 120 then drives VCM 118 to move head assembly 108 to the desired radial position over disk platter 114.
Disk platter 114 is a hard disk coated with a magnetic recording material. Data is written onto disk platter 114 when the recording material is altered by the magnetic field of write head 110. Data is read from disk platter 114 by read head 112, which senses changes in the magnetization of the recording material. During read operations, these sensed signals are amplified by preamplifier 106.
Rotation of disk platter 114 about its axis is accomplished by spindle motor 116. Servo data read from disk platter 114 is interpreted by data controller 102. Data controller 102 then sends commands to motor controller 120 to maintain a desired (e.g., constant) spindle motor speed.
Under normal circumstances, various operating modes are employed in HD system 100. These operating modes are triggered by data controller 102 and transmitted to preamplifier 106 individually (for time-critical signals) or using two- or three-wire serial port 124 (to reduce number of wires). Serial port 124 may, for example, use either the two-wire I2C or a three-wire synchronous protocol. The serial port permits selection of a multiplicity of operating conditions within preamplifier 106. Other lines (not shown) may be assigned variously to provide other preamplifier-specific control and status communication between data controller 102 and preamplifier 106.
FIG. 2 shows a more-detailed block diagram of preamplifier 106 of FIG. 1 and some of the control signals transmitted individually or via serial port lines 124 from data controller 102 to preamplifier 106. As shown in FIG. 2, preamplifier 106 includes writer circuitry 210, reader circuitry 220, and serial port interface 230. Write_Gate 201 and Dummy_Select 203 are explicit control signals transmitted directly between the data controller 102 and preamplifier 106. Standby_Select signal 205 is transmitted via serial port 124, since state-changes on this line, unlike those on the lines for Write_Gate 201 and Dummy_Select 203, are not time-critical. Certain preamplifier designs may derive Dummy_Select 205 as a command from the serial port, in which case, the Dummy_Select line would originate not in data controller 102, but in serial port 124.
Writer 210 includes write head control circuitry 212 and writer standby circuitry 214. Write head control circuitry 212 toggles current in write head 110 of FIG. 1 during write operations. Writer standby circuitry 214 powers down writer 210 when commanded to conserve power.
Reader 220 includes read head bias and low-noise amplifier (LNA) circuitry 222, dummy (read) head 224, and reader standby circuitry 226. Read head bias and LNA circuitry 222 provides MR bias current to read head 112 of FIG. 1 during read operations, and also performs low-noise amplification of the head signal. Dummy head 224 receives bias current diverted from read head 112 during periods of read head 112 inactivity (e.g., during write operations or explicit command from data controller 102). This diversion of MR bias current is performed to prolong life of the MR head by reducing electromigration degradation. Additionally, this diversion maintains adequate power in reader 220 to allow for quick powering of read head 112 by maintaining MR bias-control feedback loops close to their setpoints. Reader standby circuitry 226 powers down reader 220 when commanded to conserve power and when there is no need for fast transitions between write and read modes. Preamplifiers not requiring extremely short write-to-read transition times may omit the dummy head function, but will nonetheless generally consume more reader power during write mode than in standby mode.
Preamplifier 106 has three writer operating modes for writer 210 of FIG. 2 (write mode, pre-write mode, and standby (or sleep) mode) and three reader operating modes for reader 220 of FIG. 2 (read mode, pre-read mode, and standby (or sleep) mode).
During write mode, writer 210 is fully powered on, with write head control circuitry 212 applying to write head 110 a data-dependent write current that drives the inductive element of write head 110. During pre-write mode, writer 210 is powered on, but no write current is applied to write head 110 by write head control circuitry 212. Nevertheless, pre-write mode consumes significant power. During standby mode, writer 210 is powered down with only a relatively small trickle current being applied to writer 210.
Similarly, during read mode, reader 220 is fully powered on, with read head bias and LNA circuitry 222 applying the read bias current to read head 112, such that analog read data is received by reader 220 from read head 112 and amplified for transmission to recording channel 104. During pre-read mode, reader 220 is powered on with read head bias and LNA circuitry 222 applying the read bias current to dummy head 224 within preamplifier 106, rather than to read head 112. This diversion of MR bias current allows for quick transitions from pre-read mode to read mode, but extracts a penalty in power consumed by reader 220. Quick transitions minimize gaps in recorded data that would otherwise decrease the storage capacity of disk platter 114. During standby mode, reader 220 is powered down with only a relatively small trickle current being applied to reader 220.
Preamplifier current consumption in pre-read and pre-write modes reflects a counter-balance between power consumption and transition times between pre-read and read mode, and between pre-write and write mode. Generally, transition times can be shortened at the expense of additional power consumption.
Table I identifies the operating modes of writer 210 and reader 220 for different values of control signals Standby_Select 205, Write_Gate 201, and Dummy_Select 203 of FIG. 2, where “1” corresponds to an asserted signal and “0” corresponds to a de-asserted signal. Note that, if Standby_Select and Write_Gate are both de-asserted, then (1) writer 210 is in write mode and (2) reader 220 is in pre-read mode, independent of the value of Dummy_Select. Similarly, if Standby_Select is asserted, then both writer 210 and reader 220 are in standby mode, independent of the values of Write_Gate and Dummy_Select.
TABLE IPRIOR-ART PREAMPLIFIER OPERATING MODESControl SignalsWrite_Gate(−Write/Operating ModesStandby_Select+Read)Dummy_SelectWriterReader001/0WritePre-Read010Pre-ReadWrite011Pre-Pre-ReadWrite11/01/0StandbyStandby
For typical applications, standby mode is initiated during long periods of inactivity of preamplifier 106 by asserting Standby_Select 205. This signal is transmitted to preamplifier 106 through serial port interface 230 and applied to writer standby circuitry 214 and reader standby circuitry 226. Because of the non-time-critical nature in prior-art preamplifiers of entry into, or departure from, standby mode, it suffices to transmit the standby command through the serial port. During standby mode, writer 210 and reader 220 are both powered down to conserve power. Conserving power is very important in portable electronics and other battery-powered applications. However, a consequence of entering the power-conserving standby mode is that a relatively long transition time elapses when leaving standby mode. For this reason, prior-art readers do not enter standby mode during write operations and prior-art writers do not enter standby mode during read operations. Note that, according to Table I, if one of writer 210 and reader 220 is in standby mode, then the other is also in standby mode.
FIG. 3 graphically illustrates a possible sequence of prior-art operating modes for preamplifier 106 of FIG. 2. The scenario depicted in FIG. 3 begins at time t0 and ends at time t7. FIG. 3 shows the levels of control signals Standby_Select 205, Write_Gate 201, and Dummy_Select 203 of FIG. 2, as well as the power (i.e., reader power 302) consumed by reader circuitry 220 and the power (i.e., writer power 304) consumed by writer circuitry 210 during that time span. Note that the specific power levels shown for reader power 302 and writer power 304 are intended to be qualitative, not quantitative.
It is assumed that, at the start of the scenario (i.e., at time t0), preamplifier 106 has been dormant for an extended period of time and has previously entered standby mode. As such, Standby_Select 205 is shown at its asserted (i.e., high) level from time t0 to time t1. During this time period, reader 220 and writer 210 are almost completely powered down and receive only small trickle currents, as indicated by the low levels of both reader power 302 and writer power 304. Dummy_Select 203 and Write_Gate 201 are both asserted during this time period.
At time t1, Standby_Select 205 is de-asserted, writer 210 transitions from standby mode to pre-write mode, and reader 220 transitions from standby mode to pre-read mode. Standby_Select 205 remains de-asserted until time t7, when writer 210 and reader 220 both revert back to standby mode. Reader power 302 and writer power 304 increase at time t1 and level off at the intermediate, pre-read and pre-write mode levels, respectively. Preamplifier 106 is now prepared for quick transitions between read mode and write mode. Note that, while reader 220 is in the pre-read mode, the read bias current is diverted from read head 112 and instead applied to dummy head 224 within preamplifier 106.
Read mode is commenced at time t2, when Dummy_Select 203 is de-asserted. Note that, in read mode, the read MR bias current is applied to read head 112. Reader power 302 increases from the intermediate, pre-read mode level to the high, read mode level. Dummy_Select 203 remains de-asserted throughout the rest of the scenario of FIG. 3.
At time t3, Write_Gate 201 is de-asserted, writer 210 transitions to write mode, and reader 220 returns to pre-read mode, in which the read bias current is again diverted to dummy head 224. Reader power 302 decreases to the intermediate, pre-read mode level, and writer power 304 increases to the high, write mode level. A quick transition from write mode to read mode may now occur.
The sequencing at time t4 illustrates this quick transition from write to read. At time t4, Write_Gate 201 is asserted, thereby switching writer 210 back to pre-write mode and reader 220 back to read mode.
From time t5 to time t6, an extended write operation occurs (as indicated by the break in each graph). In particular, at time t5, Write_Gate 201 is de-asserted to switch writer 210 back to write mode and reader 220 back to pre-read mode. At time t6, Write_Gate 201 is asserted to switch writer 210 back to pre-write mode and reader 220 back to read mode.
At time t7, Standby_Select 205 is re-asserted to switch both writer 210 and reader 220 to the low-power standby mode.